This process is common to developing integrated circuits and is also used in creating FPGA’s or Field-Programmable Gate Arrays-based systems.

“Actually, the process translates higher level language into a set of elements used to create a circuit,” said Gary Meyers, CEO, a developer of EDA software and FPGA synthesis solutions.  Around two or three decades ago, when chips were smaller, circuits were developed by connecting transistors. But as chips became bigger, a different approach called gate-level or schematic capture method was adopted. Rather than connecting transistors, a group of four or five transistors were aggregated to make a logic gate and eight of them were clubbed into registers and the two groups were connected later to function as a system. “As chips started to become bigger, an even better and efficient process was needed and in the 1990’s the language-based approach was introduced,” Mr Meyers explained. He gives the “software” analogy to further clarify this approach. “We no longer write programmes at machine or assembly-level any more. We rather write them in high-level programming language like C and compile it down to the machine. For designing circuits too, we have high-level languages that can help us determine circuit behaviour. These are called Hardware Description Languages.”
Among them, Mr Meyers mentioned two languages –Verilog and VHTl—used frequently for designing FPGA circuits. He says FPGA currently operates on 65 nm (nano-metre) node, which enables makers to stuff more transistors into a chip. As a result, Mr Meyers says, designing FPGA has become complex and has to constantly look for better methods of implementing circuit designs. To address the complexities in implementing designs, Simplicity has been providing tools that works with high-level languages and makes the task effective.

Unlike ASIC’s, FPGA’s are not custom-made to perform only a set of pre-determined tasks. On the contrary, they are bought off-the-shelf and are programmed by the users for their requirements and can be re-designed. “The fact that users can implement designs and circuit behaviours much more quickly in FPGA makes it conducive for industries that put time to market over other factors,” Mr Meyers said. ASIC, on the other hand, holds the advantage when it comes to higher volumes, especially in manufacturing consumer electronic products like Ipods and digital cameras. In addition, they can also implement circuit descriptions more efficiently and therefore costs considerably less.  “Given the respective advantages, FPGA and ASIC appeal to different segments of the industry depending on their specific requirement,” he said. “So, if they look for time to market benefits, picking up FPGA would make sense, while if they want unit cost and volume advantages, ASIC is better.”

FPGA therefore becomes a natural choice for segments like communication (as they don’t ship in large volumes and need to implement custom logic in their systems) and military and aerospace, where again implementing their own designs and logic functions assume importance. And though segments like consumer electronics remain largely ASIC users, certain aspects of this –such as professional broadcast and studio equipments—are adopting FPGA for the high value it brings. Curiously enough, ASIC makers themselves are one of the major users of FPGA systems. “Since ASIC circuits are custom-made and are manufactured in a manufacturing flow at foundries, any flaw in design would mean the whole chip has to undergo a costly re-working.   So, the designs are first tested in FPGA systems for their accuracy before they are signed-off to the manufacturing process,” he said.

He pointed out that the flexibility FPGA offers to the users – for programming their designs and the facility to re-design—turns out to be a major limiting factor when it comes to performance. As FPGA systems are bought of-the-shelf and programmed by users, they have extra sets of programmable wires which slows down their performance. “While ASIC chips may run from 500 M Hz up to 1 G Hz, FPGA’s would run from 100 to 200 M Hz. While this may be comparatively slower, this is adequate for many, if not most applications,” he says.   In terms of its conformity to Moore’s Law, Mr Meyers says FPGA’s are rapidly catching up with ASIC. He says chip-makers consistently ship 65 nm chips, while a few of them have stated to cross over to 45 nm by end of next year. “One of the biggest advantage of FPGA’s is that users need not worry about signal integrity or physical effects; for ASIC this becomes a big challenge with each chip family. We even provide hardware and software conditions that takes care of issues like heat dissipation, which the user need not worry about,” he said.

However, he admitted that the more number of wires in FPGA circuits would mean they would consume more power. “Then again, if users look only for flexibility, power is one more issue. The most interesting development in this aspect is the fact that a lot of traditional ASIC designers are migrating to FPGA and they bring with them the capability to work on the power issue. So, we don’t see why there shouldn’t be a solution to this problem in the near future,” he said.